Patents
Name Application Number
SOI Semiconductor Structure with a Hybrid of Coplanar Germanium and III-V, and Preparation Method thereof 13636128
Hexagonal Boron Nitride Substrate With Monatomic Layer Step, And Preparation Method And Application Thereof 13580267
THE APPARATUS AND METHOD OF POWER MEASUREMENT FOR PULSED TERAHERTZ QUANTUM-CASCADE LASER 13641777
METHOD OF NISIGE EPITAXIAL GROWTH BY INTRODUCING AL INTERLAYER 13260757
METHOD OF FABRICATING HIGH-MOBILITY DUAL CHANNEL MATERIAL BASED ON SOI SUBSTRATE 13262656
DATA READOUT CIRCUIT OF PHASE CHANGE MEMORY 13202963
PHASE CHANGE MEMORY STRUCTURE HAVING LOW-K DIELECTRIC HEAT-INSULATING MATERIAL AND FABRICATION METHOD THEREOF 13202955
AL-SB-TE PHASE CHANGE MATERIAL USED FOR PHASE CHANGE MEMORY AND FABRICATION METHOD THEREOF 13202953
PHASE CHANGE MEMORY CELL AND FABRICATION METHOD THEREOF 13202697
CHEMICAL MECHANICAL POLISHING SLURRY 13202669
METHOD OF EPITAXIAL GROWTH EFFECTIVELY PREVENTING AUTO-DOPING EFFECT 13202944
METHOD OF FABRICATING DUAL TRENCH ISOLATED EPITAXIAL DIODE ARRAY 13203135
METHOD OF DEPOSITING GATE DIELECTRIC, METHOD OF PREPARING MIS CAPACITOR, AND MIS CAPACITOR 13256435
METHOD OF FABRICATING GRAPHENE BASED FIELD EFFECT TRANSISTOR 13145033
METHOD OF FABRICATING SOI SUPER-JUNCTION LDMOS STRUCTURE CAPABLE OF COMPLETELY ELIMINATING SUBSTRATE-ASSISTED DEPLETION EFFECTS 13203724